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| 16Mb: x16 IT SDRAM SYNCHRONOUS DRAM FEATURES * PC100 functionality * Fully synchronous; all signals registered on positive edge of system clock * Internal pipelined operation; column address can be changed every clock cycle * Internal banks for hiding row access/precharge 1 Meg x 16 - 512K x 16 x 2 banks architecture with 11 row, 8 column addresses per bank * Programmable burst lengths: 1, 2, 4, 8 or full page * Auto Precharge Mode, includes CONCURRENT AUTO PRECHARGE * Self Refresh and Adaptable Auto Refresh Modes - 32ms, 2,048-cycle refresh or - 64ms, 2,048-cycle refresh or - 64ms, 4,096-cycle refresh * LVTTL-compatible inputs and outputs * Single +3.3V 0.3V power supply * Supports CAS latency of 1, 2 and 3 * Industrial temperature range: -40C to +85C MT48LC1M16A1 SIT - 512K x 16 x 2 banks INDUSTRIAL TEMPERATURE For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/sdramds.html PIN ASSIGNMENT (Top View) 50-Pin TSOP VDD DQ0 DQ1 VssQ DQ2 DQ3 VDDQ DQ4 DQ5 VssQ DQ6 DQ7 VDDQ DQML WE# CAS# RAS# CS# BA A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Vss DQ15 DQ14 VssQ DQ13 DQ12 VDDQ DQ11 DQ10 VssQ DQ9 DQ8 VDDQ NC DQMH CLK CKE NC A9 A8 A7 A6 A5 A4 Vss OPTIONS * Configuration 1 Meg x 16 (512K x 16 x 2 banks) * Plastic Package - OCPL* 50-pin TSOP (400 mil) * Timing (Cycle Time) 6ns (166 MHz) 7ns (143 MHz) 8ns (125 MHz) MARKING 1M16A1 Note: The # symbol indicates signal is active LOW. Configuration Refresh Count Row Addressing Bank Addressing Column Addressing 1 Meg x 16 512K x 16 x 2 banks 2K or 4K 2K (A0-A10) 2 (BA) 256 (A0-A7) TG -6 -7 -8A 16MB (X16) SDRAM PART NUMBER PART NUMBER MT48LC1M16A1TG SIT ARCHITECTURE 1 Meg x 16 * Refresh 2K or 4K with Self Refresh Mode at 64ms * Operating Temperature -40C to +85C Part Number Example: S IT KEY TIMING PARAMETERS SPEED -6 -7 -8A CLOCK 166 MHz 143 MHz 125 MHz ACCESS TIME CL = 3** 5.5ns 5.5ns 6ns SETUP 2ns 2ns 2ns HOLD 1ns 1ns 1ns MT48LC1M16A1TG-7SIT *Off-center parting line **CL = CAS (READ) latency 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM GENERAL DESCRIPTION The 16Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 16,777,216 bits. It is internally configured as a dual 512K x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16-bit banks is organized as 2,048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA selects the bank, A0-A10 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 1 Meg x 16 SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing the alternate bank will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. The 1 Meg x 16 SDRAM is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM TABLE OF CONTENTS Functional Block Diagram - 1 Meg x 16 ................. 3 Pin Descriptions ........................................................ 4 Functional Description ........................................ Initialization ........................................................ Register Definitions ............................................. Mode Register ................................................ Burst Length .............................................. Burst Type ................................................. CAS Latency .............................................. Operating Mode ....................................... Write Burst Mode ..................................... Commands .............................................................. Truth Table 1 (Commands and DQM Operation) .............. Command Inhibit ............................................... No Operation (NOP) .......................................... Load Mode Register ............................................ Active .................................................................. Read .................................................................. Write .................................................................. Precharge ............................................................. Auto Precharge .................................................... Burst Terminate ................................................... Auto Refresh ........................................................ Self Refresh .......................................................... Operation ................................................................ Bank/Row Activation ......................................... Reads .................................................................. Writes .................................................................. Precharge ............................................................. Power-Down ....................................................... Clock Suspend .................................................... Burst Read/Single Write ...................................... 5 5 5 5 5 5 7 7 7 8 8 9 9 9 9 9 9 9 9 9 10 10 11 11 12 18 20 20 21 21 Concurrent Auto Precharge ................................ Truth Table 2 (CKE) ................................................... Truth Table 3 (Current State, Same Bank) ....................... Truth Table 4 (Current State, Different Bank) ................... Absolute Maximum Ratings .................................... DC Electrical Characteristics and Operating Conditions ........................................... IDD Specifications and Conditions .......................... Capacitance .............................................................. Timing Waveforms Initialize and Load Mode Register ...................... Power-Down Mode ............................................ Clock Suspend Mode .......................................... Auto Refresh Mode ............................................. Self Refresh Mode ............................................... Reads Read - Single Read ......................................... Read - Without Auto Precharge .................... Read - With Auto Precharge .......................... Alternating Bank Read Accesses .................... Read - Full-Page Burst .................................... Read - DQM Operation ................................. Writes Write - Single Write ....................................... Write - Without Auto Precharge ................... Write - With Auto Precharge ......................... Alternating Bank Write Accesses ................... Write - Full-Page Burst ................................... Write - DQM Operation ................................ 22 24 25 27 29 29 29 30 AC Electrical Characteristics (Timing Table) .... 30 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM FUNCTIONAL BLOCK DIAGRAM 1 Meg x 16 SDRAM ROW DECODER 11 ROWADDRESS LATCH 11 2,048 BANK0 MEMORY ARRAY (2,048 x 256 x 16) CKE CLK DQML, DQMH WE# CAS# RAS# COMMAND DECODE CS# CONTROL LOGIC 256 (x16) SENSE AMPLIFIERS I/O GATING DQM MASK LOGIC MODE REGISTER 256 16 DATA OUTPUT REGISTER 12 8 COLUMNADDRESS BUFFER BURST COUNTER COLUMNADDRESS LATCH 8 COLUMN DECODER 16 16 DQ0DQ15 DATA INPUT 8 REGISTER 256 A0-A10, BA 12 ADDRESS REGISTER REFRESH CONTROLLER SENSE AMPLIFIERS I/O GATING DQM MASK LOGIC 11 ROWADDRESS MUX REFRESH COUNTER 256 (x16) 11 ROW DECODER 11 ROWADDRESS LATCH 11 2,048 BANK1 MEMORY ARRAY (2,048 x 256 x 16) 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM PIN DESCRIPTIONS PIN NUMBERS 35 SYMBOL CLK TYPE DESCRIPTION Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE in either bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters powerdown and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Input Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered. Input Input/Output Mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. DQML corresponds to DQ0-DQ7; DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM. 34 CKE 18 CS# 15, 16, 17 14, 36 WE#, CAS#, RAS# DQML, DQMH 19 BA Input Bank Address Inputs: BA defines to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. BA is also used to program the twelfth bit of the Mode Register. Input Address Inputs: A0-A10 are sampled during the ACTIVE command (row-address A0-A10) and READ/WRITE command (column-address A0A7, with A10 defining AUTO PRECHARGE) to select one location out of the 512K available in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Input/ Data I/Os: Data bus. Output - No Connect: These pins should be left unconnected. 21-24, 27-32, 20 A0-A10 2, 3, 5, 6, 8, 9, 11, 12, 39, 40, 42, 43, 45, 46, 48, 49 33, 37 7, 13, 38, 44 4, 10, 41, 47 1, 25 26, 50 DQ0DQ15 NC VDDQ VSSQ VDD VSS Supply DQ Power: Provide isolated power to DQs for improved noise immunity. Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. Supply Power Supply: +3.3V 0.3V. Supply Ground. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM FUNCTIONAL DESCRIPTION In general, the SDRAM is a dual 512K x 16 DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16-bit banks is organized as 2,048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA selects the bank, A0-A10 select the row). The address bits (A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Register Definition MODE REGISTER The Mode Register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 1. The Mode Register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode Register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a fullpage burst is available for the sequential type. The fullpage burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two, by A2-A7 when the burst length is set to four and by A3A7 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to applying any command other than a COMMAND INHIBIT or a NOP. Starting at some point during this 100s period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100s delay has been satisfied, with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Table 1 Burst Definition Burst Length Starting Column Order of Accesses Within a Burst Address Type = Sequential Type = Interleaved A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported 11 10 9 8 7 6 5 4 BT 3 2 1 0 Mode Register (Mx) Reserved* WB Op Mode CAS Latency Burst Length *Should program M11, M10 = 0, 0 to ensure compatibility with future devices. M2 M1M0 000 001 010 011 100 101 110 111 Burst Length M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved 2 4 M3 0 1 Burst Type Sequential Interleave 8 M6 M5M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved Full Page (256) 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 n = A0-A7 Cn+3, Cn+4... ...Cn-1, (location 0-255) Cn... M8 0 - M7 0 - M6 - M0 Defined - Operating Mode Standard Operation All other states reserved M9 0 1 Write Burst Mode Programmed Burst Length Single Location Access Figure 1 Mode Register Definition NOTE: 1. For a burst length of two, A1-A7 select the block of two burst; A0 selects the starting column within the block. 2. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block. 3. For a burst length of eight, A3-A7 select the block of eight burst; A0-A2 select the starting column within the block. 4. For a full-page burst, the full row is selected and A0-A7 select the starting column. 5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. For a burst length of one, A0-A7 select the unique column to be accessed, and Mode Register bit M3 is ignored. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to 1, 2 or 3 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0, and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. T0 CLK COMMAND T1 T2 READ tLZ NOP tOH DOUT DQ tAC CAS Latency = 1 T0 CLK COMMAND T1 T2 T3 Table 2 CAS Latency ALLOWABLE OPERATING FREQUENCY (MHz) SPEED -6 -7 -8A CAS LATENCY = 1 50 40 40 CAS CAS LATENCY = 2 LATENCY = 3 125 100 77 166 143 125 READ NOP tLZ NOP tOH DOUT DQ tAC CAS Latency = 2 T0 CLK COMMAND T1 T2 T3 T4 READ NOP NOP tLZ NOP tOH DOUT DQ tAC CAS Latency = 3 DON'T CARE UNDEFINED Figure 2 CAS Latency 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM COMMANDS Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Operation section; these tables provide current state/next state information. TRUTH TABLE 1 - COMMANDS AND DQM OPERATION (Notes: 1) NAME (FUNCTION) COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column and start READ burst) WRITE (Select bank and column and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z NOTE: 1. 2. 3. 4. 5. 6. 7. 8. CS# RAS# CAS# WE# DQM ADDR H L L L L L L L L - - X H L H H H L L L - - X H H L L H H L L - - X H H H L L L H L - - X X X L/H8 L/H8 X X X X L H X X Bank/Row Bank/Col DQs NOTES X X X X 3 4 4 Bank/Col Valid X Code X Op-Code - - Active X X X Active High-Z 5 6, 7 2 8 8 CKE is HIGH for all commands shown except SELF REFRESH. A0-A10 and BA define the op-code written to the Mode Register. A0-A10 provide row address, and BA determines which bank is made active. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA determines which bank is being read from or written to. For A10 LOW, BA determines which bank is being precharged; for A10 HIGH, all banks are precharged and BA is a "Don't Care." This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The Mode Register is loaded via inputs A0-A10 and BA. See Mode Register heading in Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA input selects the bank, and the address provided on inputs A0-A10 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA input selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs, subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA input selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, input BA selects the bank. Otherwise BA is treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. AUTO PRECHARGE AUTO PRECHARGE is a feature which performs the same individual-bank PRECHARGE function described above, but without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where AUTO PRECHARGE does not apply. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. AUTO PRECHARGE ensures that the PRECHARGE is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated as shown in the Operation section of this data sheet. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORERAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing during an AUTO REFRESH command is generated by an internal refresh controller. This means that the address lines are not used to generate the refresh address, and are "Don't Care". The 1 Meg x 16 SDRAM requires 2,048 AUTO REFRESH cycles every 64ms (tREF) to ensure that each row is refreshed. Distributed refresh would be achieved by providing an AUTO REFRESH command once every 31.25s. Burst refresh could be accomplished by issuing 2,048 AUTO REFRESH commands consecutively at the minimum cycle rate of tRC. To provide a 4K refresh scheme, the refresh rate would be doubled. Thus, 2,048 AUTO-REFRESH commands distributed every 15.625s would allow the 1 Meg x 16 SDRAM to have a 4K refresh if required. Of the three types of refreshs options, utilizing the 2,048 cycles every 64ms (31.25s per refresh) provides the maximum power savings. SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become "Don't Care," with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS, and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR, because time is required for the completion of any internal refresh in progress. Upon exiting self refresh mode, AUTO REFRESH commands may be issued every 15.625s or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 3). After opening a row (issuing an ACTIVE command) a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be issued. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks rounded to 3. This is reflected in Figure 4, which covers any case where 2 < tRCD (MIN)/tCK 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. T0 CLK T1 CLK CKE CS# HIGH RAS# CAS# WE# A0-A10 ROW ADDRESS BANK 1 BA BANK 0 Figure 3 Activating a Specific Row in a Specific Bank T2 T3 T4 COMMAND ACTIVE NOP NOP READ or WRITE tRCD DON'T CARE EXAMPLE: Meeting tRCD Figure 4 (MIN) when 2 < tRCD (MIN)/tCK 3 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM READs READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are provided with the READ command and AUTO PRECHARGE is either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, AUTO PRECHARGE is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go HighZ. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). Data from any READ burst may be truncated with a subsequent READ command, and data from a fixedlength READ burst may be immediately followed by data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst, or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired T0 T1 T2 CLK CKE CS# HIGH CLK COMMAND READ tLZ NOP tOH DOUT DQ tAC CAS Latency = 1 RAS# T0 T1 T2 T3 CAS# CLK COMMAND READ NOP tLZ NOP tOH DOUT WE# DQ tAC A0-A7 A8-A9 COLUMN ADDRESS CAS Latency = 2 T0 T1 T2 T3 T4 ENABLE AUTO PRECHARGE CLK COMMAND A10 DISABLE AUTO PRECHARGE READ NOP NOP tLZ NOP tOH DOUT BANK 1 DQ tAC CAS Latency = 3 BA BANK 0 DON'T CARE Figure 5 READ Command Figure 6 CAS Latency 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 UNDEFINED 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM data element is valid, where x equals the CAS latency minus one. This is shown in Figure 7 for READ latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 1 Meg x 16 SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed, random read accesses within a page can be performed as shown in Figure 8. T0 CLK T1 T2 T3 T4 T5 COMMAND READ NOP NOP NOP READ X = 0 cycles NOP ADDRESS BANK, COL n BANK, COL b DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b CAS Latency = 1 T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ NOP NOP NOP READ NOP NOP X = 1 cycle ADDRESS BANK, COL n BANK, COL b DQ CAS Latency = 2 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND READ NOP NOP NOP READ NOP NOP NOP X = 2 cycles ADDRESS BANK, COL n BANK, COL b DQ CAS Latency = 3 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b NOTE: Each READ command may be to either bank. DQM is LOW. DON'T CARE Figure 7 Consecutive READ Bursts 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM T0 CLK T1 T2 T3 T4 COMMAND READ READ READ READ NOP ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DQ CAS Latency = 1 DOUT n DOUT a DOUT x DOUT m T0 CLK T1 T2 T3 T4 T5 COMMAND READ READ READ READ NOP NOP ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DQ CAS Latency = 2 DOUT n DOUT a DOUT x DOUT m T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ READ READ READ NOP NOP NOP ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DQ CAS Latency = 3 DOUT n DOUT a DOUT x DOUT m NOTE: Each READ command may be to either bank. DQM is LOW. DON'T CARE Figure 8 Random READ Accesses 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a subsequent WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be the possibility that the device driving the input data would go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention as shown in Figures 9 and 10. The DQM signal must be asserted (HIGH) at least two clocks (DQM latency is two clocks for output buffers) prior to the WRITE command to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z) regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 10, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted (DQM latency is zero clocks for input buffers) prior to the WRITE command to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 10 shows the case where the additional NOP is needed. T0 CLK DQM T1 T2 T3 T4 T0 CLK DQM T1 T2 T3 T4 T5 COMMAND ADDRESS READ NOP NOP NOP WRITE COMMAND ADDRESS READ NOP NOP NOP NOP WRITE BANK, COL n BANK, COL b BANK, COL n BANK, COL b tCK tHZ DQ DOUT n DIN b tHZ DQ DOUT n DIN b tDS NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. DON'T CARE tDS NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required. Figure 9 READ to WRITE Figure 10 READ to WRITE with Extra Clock Cycle 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO PRECHARGE was not activated) and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 11 for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same T0 CLK T1 T2 T3 T4 T5 T6 T7 t RP COMMAND READ NOP NOP NOP PRECHARGE X = 0 cycles NOP NOP ACTIVE ADDRESS BANK a, COL n BANK (a or all) BANK a, ROW DQ CAS Latency = 1 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 T0 CLK T1 T2 T3 T4 T5 T6 T7 t RP COMMAND READ NOP NOP NOP PRECHARGE X = 1 cycle NOP NOP ACTIVE ADDRESS BANK a, COL n BANK (a or all) BANK a, ROW DQ CAS Latency = 2 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 T0 CLK T1 T2 T3 T4 T5 T6 T7 t RP COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE X = 2 cycles ADDRESS BANK a, COL n BANK (a or all) BANK a, ROW DQ CAS Latency = 3 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 NOTE: DQM is LOW. DON'T CARE Figure 11 READ to PRECHARGE 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM operation that would result from the same fixedlength burst with AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that AUTO PRECHARGE was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 12 for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst. T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ NOP NOP NOP BURST TERMINATE X = 0 cycles NOP NOP ADDRESS BANK, COL n DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 CAS Latency = 1 T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ NOP NOP NOP BURST TERMINATE X = 1 cycle NOP NOP ADDRESS BANK, COL n DQ CAS Latency = 2 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND READ NOP NOP NOP BURST TERMINATE NOP NOP NOP X = 2 cycles ADDRESS BANK, COL n DQ CAS Latency = 3 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 NOTE: DQM is LOW. DON'T CARE Figure 12 Terminating a READ Burst 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are provided with the WRITE command and AUTO PRECHARGE is either enabled or disabled for that access. If AUTO PRECHARGE is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, AUTO PRECHARGE is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z, and any additional input data will be ignored (see Figure 14). A full-page burst will continue until terminated. (At the end of the page it will wrap to column 0 and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixedlength WRITE burst may be immediately followed by data for a subsequent WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 15. Data n + 1 is either the last of a burst of two, or the last desired of a longer burst. The 1 Meg x 16 SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed, random write accesses within a page can be performed as shown in Figure 16. T0 CLK T1 T2 T3 COMMAND WRITE NOP NOP NOP ADDRESS BANK, COL n DQ DIN n DIN n+1 NOTE: Burst length = 2. DQM is LOW. CLK CKE CS# HIGH Figure 14 WRITE Burst T0 CLK T1 T2 RAS# CAS# COMMAND WRITE NOP WRITE WE# ADDRESS A0-A7 A8-A9 ENABLE AUTO PRECHARGE COLUMN ADDRESS BANK, COL n BANK, COL b DQ DIN n DIN n+1 DIN b A10 DISABLE AUTO PRECHARGE NOTE: BANK 1 DQM is LOW. Each WRITE command may be to any bank. DON'T CARE BA BANK 0 Figure 13 WRITE Command 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 Figure 15 WRITE to WRITE 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixedlength WRITE burst may be immediately followed by a subsequent READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in Figure 17. Data n + 1 is either the last of a burst of two, or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO PRECHARGE was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 18. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixedlength burst with AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. T0 CLK T1 T2 T3 COMMAND WRITE WRITE WRITE WRITE CLK T0 T1 T2 T3 T4 T5 tWR = 1 CLK (tCK tWR) ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DQM t RP DQ NOTE: DIN n DIN a DIN x DIN m COMMAND WRITE NOP PRECHARGE NOP NOP ACTIVE Each WRITE command may be to any bank. DQM is LOW. ADDRESS BANK a, COL n t WR BANK (a or all) BANK a, ROW DQ Figure 16 Random WRITE Cycles T0 CLK T1 T2 T3 T4 T5 DIN n DIN n+1 tWR = 2 CLK (tCK < tWR) DQM t RP COMMAND COMMAND WRITE NOP READ NOP NOP NOP WRITE NOP NOP PRECHARGE NOP ACTIVE ADDRESS ADDRESS BANK, COL n BANK, COL b BANK a, COL n t WR BANK (a or all) BANK a, ROW DQ DOUT b DOUT b+1 DIN n DIN n+1 DQ NOTE: DIN n DIN n+1 NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Future SDRAMs will require a tWR of at least two clocks. DON'T CARE The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW. CAS latency = 2 for illustration. Figure 17 WRITE to READ 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 Figure 18 WRITE to PRECHARGE 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 19, where data n is the last desired data element of a longer burst. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks (see Figure 20). The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, input BA selects the bank. When all banks are to be precharged, input BA is treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. POWER-DOWN POWER-DOWN occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT, when no accesses are in progress (see Figure 21). If POWERDOWN occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the powerdown state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). T0 CLK T1 T2 COMMAND WRITE BURST TERMINATE Next Command ADDRESS BANK, COL n (Address) DQ DIN n (Data) NOTE: DQMs are low Figure 19 Terminating a WRITE Burst CLK CKE CS# HIGH CLK tCKS (( )) (( )) < tCKS RAS# CKE (( )) CAS# COMMAND NOP (( )) (( )) NOP ACTIVE All banks idle Input buffers gated off WE# Enter POWERDOWN mode Exit POWERDOWN mode tRCD tRAS tRC A0-A9 DON'T CARE BANK 0 and 1 A10 BANK 0 or 1 BANK 1 Figure 21 POWER-DOWN BA BANK 0 Figure 20 PRECHARGE Command 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM CLOCK SUSPEND The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge are ignored; any data present on the DQ pins will remain driven; and burst counters are not incremented as long as the clock is suspended (see examples in Figures 22 and 23). Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the Mode Register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one) regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). T0 CLK T1 T2 T3 T4 T5 CLK T0 T1 T2 T3 T4 T5 T6 CKE CKE INTERNAL CLOCK INTERNAL CLOCK COMMAND READ NOP NOP NOP NOP NOP COMMAND NOP WRITE NOP NOP ADDRESS BANK, COL n ADDRESS BANK, COL n DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DQ DIN n DIN n+1 DIN n+2 NOTE: For this example, burst length = 4 or greater, and DQM is LOW. NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and DQM is LOW. DON'T CARE Figure 22 Clock Suspend During WRITE Burst Figure 23 Clock Suspend During READ Burst 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with AUTO PRECHARGE enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. READ with AUTO PRECHARGE 1. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24). 2. Interrupted by a WRITE (with or without AUTO PRECHARGE): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25). T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND BANK n NOP READ - AP BANK n NOP READ - AP BANK m NOP NOP NOP NOP Page Active READ with Burst of 4 Interrupt Burst, Precharge t RP - BANK n Idle tRP - BANK m Precharge Internal States BANK m Page Active READ with Burst of 4 ADDRESS DQ BANK n, COL a BANK m, COL d DOUT a DOUT a+1 DOUT d DOUT d+1 CAS Latency = 3 (BANK n) CAS Latency = 3 (BANK m) NOTE: DQM is LOW. Figure 24 READ with AUTO PRECHARGE Interrupted by a READ T0 CLK READ - AP BANK n Page Active WRITE - AP BANK m T1 T2 T3 T4 T5 T6 T7 COMMAND BANK n NOP NOP NOP NOP NOP NOP READ with Burst of 4 Interrupt Burst, Precharge tRP - BANK n Idle t WR - BANK m Write-Back Internal States BANK m BANK n, COL a Page Active WRITE with Burst of 4 ADDRESS 1 DQM DQ BANK m, COL d DOUT a CAS Latency = 3 (BANK n) DIN d DIN d+1 DIN d+2 DIN d+3 NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4. DON'T CARE Figure 25 READ with AUTO PRECHARGE Interrupted by a WRITE 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM WRITE with AUTO PRECHARGE 3. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a WRITE on bank n when registered, with the dataout appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26). 4. Interrupted by a WRITE (with or without AUTO PRECHARGE): A WRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (Figure 27). T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND BANK n NOP WRITE - AP BANK n NOP READ - AP BANK m NOP NOP NOP NOP Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back tWR - BANK n Precharge tRP - BANK n tRP - BANK m Internal States BANK m Page Active READ with Burst of 4 ADDRESS DQ BANK n, COL a DIN a DIN a+1 BANK m, COL d DOUT d CAS Latency = 3 (BANK m) DOUT d+1 NOTE: 1. DQM is LOW. Figure 26 WRITE with AUTO PRECHARGE Interrupted by a READ T0 CLK WRITE - AP BANK n WRITE - AP BANK m T1 T2 T3 T4 T5 T6 T7 COMMAND BANK n NOP NOP NOP NOP NOP NOP Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back tWR - BANK n Precharge tRP - BANK n t WR - BANK m Write-Back Internal States BANK m Page Active WRITE with Burst of 4 ADDRESS DQ NOTE: 1. DQM is LOW. BANK n, COL a DIN a DIN a+1 DIN a+2 BANK m, COL d DIN d DIN d+1 DIN d+2 DIN d+3 DON'T CARE Figure 27 WRITE with AUTO PRECHARGE Interrupted by a WRITE 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM TRUTH TABLE 2 - CKE (Notes: 1-4) CKEn-1 CKEn L L CURRENT STATE Power-Down Self Refresh Clock Suspend L H Power-Down Self Refresh Clock Suspend H L All Banks Idle All Banks Idle Reading or Writing H NOTE: 1. 2. 3. 4. 5. COMMAND n X X X COMMAND INHIBIT or NOP COMMAND INHIBIT or NOP X COMMAND INHIBIT or NOP AUTO REFRESH VALID See Truth Table 3 ACTION n Maintain Power-Down Maintain Self Refresh Maintain Clock Suspend Exit Power-Down Exit Self Refresh Exit Clock Suspend Power-Down Entry Self Refresh Entry Clock Suspend Entry NOTES 5 6 7 H CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state of the SDRAM immediately prior to clock edge n. COMMANDn is the command registered at clock edge n and ACTIONn is a result of COMMANDn. All states and sequences not shown are illegal or reserved. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting SELF REFRESH at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM TRUTH TABLE 3 - CURRENT STATE BANK n - COMMAND TO BANK n (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any H L L Idle L L L L Row Active Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) L L L L L L L L L L X H L L L L H H L H H L H H H L H X H H L L H L L H L L H H L L H H X H H H L L H L L H L L L H L L L COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) ACTIVE (Select and activate row) AUTO REFRESH LOAD MODE REGISTER PRECHARGE READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Truncate READ burst, start PRECHARGE) BURST TERMINATE READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE (Truncate WRITE burst, start PRECHARGE) BURST TERMINATE 7 7 11 10 10 8 10 10 8 9 10 10 8 9 NOTES NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged and tRP has been met. Row Active: A row in the bank has been activated and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank, should be issued on any clock edge occuring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/Auto Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when t RP has been met. Once tRP is met, the bank will be in the idle state. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM NOTE (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM TRUTH TABLE 4 - CURRENT STATE BANK n - COMMAND TO BANK m (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle Row Activating, Active or Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (With Auto Precharge) Write (With Auto Precharge) H L X L L L L L L L L L L L L L L L L L L L L X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H X H X H H L L H H L L H H L L H H L L H H L L COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Any command otherwise allowed to bank m ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE 7, 8, 16 7, 8, 17 9 7, 8, 14 7, 8, 15 9 7, 12 7, 13 9 7, 10 7, 11 9 7 7 NOTES NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged and tRP has been met. Row Active: A row in the bank has been activated and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Read w/Auto Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when t RP has been met. Once tRP is met, the bank will be in the idle state. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM NOTE (continued): 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been interrupted by bank m's burst. 9. Burst in bank n continues as initiated. 10. For a READ without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 7). 11. For a READ without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. For a WRITE without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 14. For a READ with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24). 15. For a READ with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25). 16. For a WRITE with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26). 17. For a WRITE with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 27). 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM ABSOLUTE MAXIMUM RATINGS* Voltage on VDD, VDDQ Supply Relative to VSS ................................ -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS ................................ -1V to +4.6V Operating Temperature, TA (ambient) -40C to +85C Storage Temperature (plastic) .......... -55C to +150C Power Dissipation .................................................. 1W *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 6) (-40C TA +85C; VDD, VDDQ = +3.3V 0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V VIN VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) SYMBOL VDD, VDDQ VIH VIL II IOZ VOH VOL MIN 3 2.2 -0.3 -5 -10 2.4 - MAX 3.6 VDD + 0.3 0.8 5 10 - 0.4 UNITS NOTES V V V A A V V 22 22 IDD SPECIFICATIONS AND CONDITIONS (Notes: 1, 6, 11, 13) (-40C TA +85C; VDD, VDDQ = +3.3V 0.3V) PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN); CAS latency = 3 STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle STANDBY CURRENT: Active Mode; CS# = HIGH; CKE = HIGH; All banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All banks active, CAS latency = 3 AUTO REFRESH CURRENT: tRC = 15.625s; CAS latency = 3; CS# = HIGH; CKE = HIGH SELF REFRESH CURRENT: CKE 0.2V SYMBOL IDD1 -6 145 MAX -7 140 -8A 135 UNITS NOTES mA 3, 18, 19, 26 26 3, 12, 19, 26 3, 18, 19, 26 3, 12, 18, 19, 26 4 IDD2 IDD3 2 45 2 40 2 35 mA mA IDD4 IDD5 140 45 130 40 100 35 mA mA IDD6 1 1 1 mA 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM CAPACITANCE PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs SYMBOL MIN CI1 CI2 CIO 2.5 2.5 4.0 MAX UNITS NOTES 4.0 5.0 6.5 pF pF pF 2 2 2 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 5, 6, 8, 9, 11) (-40C TA +85C) AC CHARACTERISTICS PARAMETER Access time from CLK (pos. edge) -6 -7 -8A SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES tAC 5.5 5.5 6 ns tAC 8 8.5 9 ns 22 tAC 18 22 22 ns 22 tAH 1 1 1 ns tAS 2 2 2 ns tCH 2.5 2.75 3 ns tCL 2.5 2.75 3 ns tCK 6 7 8 ns 23 tCK 8 10 13 ns 22, 23 tCK 20 25 25 ns 23 tCKH 1 1 1 ns tCKS 2 2 2 ns tCMH 1 1 1 ns tCMS 2 2 2 ns tDH 1 1 1 ns tDS 2 2 2 ns tHZ 5.5 5.5 6 ns 10 tHZ 6 8.5 9 ns 10 tHZ 18 22 22 ns 10 tLZ 1 1 1 ns tOH 1.5 1.5 1.5 ns tRAS 42 120,000 42 120,000 48 120,000 ns tRC 60 70 80 ns 22 tRCAR 66 70 80 ns tRCD 18 20 24 ns 22 tREF 64 64 64 ms tRP 18 21 24 ns 22 tRRD 12 14 16 ns tT 0.3 1.2 0.3 1.2 0.3 10 ns 7 tWR tCK 1 + 4ns 1 + 3ns 1 + 2ns 24 10 10 10 ns 25 tXSR 80 80 80 ns 20 CL = 3 CL = 2 CL = 1 Address hold time Address setup time CLK high level width CLK low level width Clock cycle time CL = 3 CL = 2 CL = 1 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time CL = 3 CL = 2 CL = 1 Data-out low-impedance time Data-out hold time ACTIVE to PRECHARGE command AUTO REFRESH, ACTIVE command period AUTO REFRESH period ACTIVE to READ or WRITE delay Refresh period - 2,048 or 4,096 rows PRECHARGE command period ACTIVE bank A to ACTIVE bank B command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM AC FUNCTIONAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 11) (-40C TA +85C) PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDAL tDAL tDPL tBDL tCDL tRDL tMRD tROH tROH tROH -6 1 1 1 0 0 2 0 5 4 3 2 0 1 1 2 3 2 1 -7 1 1 1 0 0 2 0 5 4 3 2 0 1 1 2 3 2 1 -8A 1 1 1 0 0 2 0 5 4 3 2 0 1 1 2 3 2 1 UNITS tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK NOTES 17 14 14 17 17 17 17 15, 21 15, 21 15, 21 16 17 17 16, 21 26 17 17 17 CL = 3 CL = 2 CL = 1 Data-in to PRECHARGE Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 CL = 1 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM NOTES 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, tA = 25C. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-40C TA +85C) is ensured. 6. An initial pause of 100s is required after powerup, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: 12.Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid VIH or VIL levels. 13.IDD specifications are tested after the device is properly initialized. 14.Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15.Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16.Timing actually specified by tWR. 17.Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18.The IDD current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 19.Address transitions average one transition every two-clock period. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 166 MHz for -6, 143 MHz for -7 and 125 MHz for -8A. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns. The pulse width cannot be greater than one third of the cycle rate. 23.The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24.Auto precharge mode only. 25.Precharge mode only. 26. tCK = 6ns for -6, 7ns for -7, 8ns for -8A. Q 30pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V with timing referenced to 1.5V crossover point. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM INITIALIZE AND LOAD MODE REGISTER T0 CLK (( )) tCKS (( )) (( )) T1 tCK tCKH (( )) (( )) (( )) (( )) Tn + 1 tCH (( )) (( )) To + 1 tCL (( )) (( )) Tp + 1 Tp + 2 Tp + 3 CKE (( )) (( )) tCMH COMMAND (( )) NOP (( )) tCMS PRECHARGE (( )) (( )) AUTO REFRESH (( )) NOP NOP (( )) (( )) (( )) (( )) (( )) AUTO REFRESH (( )) NOP NOP (( )) (( )) (( )) (( )) (( )) LOAD MODE REGISTER NOP ACTIVE DQM1 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) tAS tAH BANK, ROW ADDRESS BANK(S) CODE DQ High-Z (( )) T=100s (MIN) (( )) tRP tRCAR tRC tMRD Power-up: VDD and CLK stable. Precharge all banks. AUTO REFRESH AUTO REFRESH Program Mode Register.2, 3 DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) tCKH -7 MAX MIN 1 2 2.75 2.75 7 10 25 1 MAX MIN 1 2 3 3 8 13 25 1 MIN 1 2 2.5 2.5 6 8 20 1 -8A MAX -6 UNITS ns ns ns ns ns ns ns ns SYMBOL* tCKS tCMH tCMS tMRD tRC tRCAR tRP -7 MAX MIN 2 1 2 2 70 70 21 MAX MIN 2 1 2 2 80 80 24 MIN 2 1 2 2 60 66 18 -8A MAX UNITS ns ns ns tCK ns ns ns *CAS latency indicated in parentheses. NOTE: 1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. 2. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired. 3. Outputs are guaranteed High-Z after command is issued. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM POWER-DOWN MODE 1 T0 CLK tCK T1 tCL tCKS CKE tCKS tCMS COMMAND tCKH tCMH NOP NOP (( )) (( )) (( )) (( )) T2 tCH (( )) (( )) Tn + 1 Tn + 2 tCKS (( )) PRECHARGE NOP ACTIVE DQM2 tAS ADDRESS tAH BANK(S) High-Z (( )) (( )) (( )) BANK, ROW DQ Two clock cycles Precharge all active banks. Input buffers gated off while in power-down mode. All banks idle. Exit power-down mode. DON'T CARE UNDEFINED All banks idle, enter power-down mode. TIMING PARAMETERS -6 SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) -7 MAX MIN 1 2 2.75 2.75 7 10 MAX MIN 1 2 3 3 8 13 MIN 1 2 2.5 2.5 6 8 -8A MAX -6 UNITS ns ns ns ns ns ns SYMBOL* tCK (1) tCKH tCKS tCMH tCMS -7 MAX MIN 25 1 2 1 2 MAX MIN 25 1 2 1 2 -8A MAX UNITS ns ns ns ns ns MIN 20 1 2 1 2 *CAS latency indicated in parentheses. NOTE: 1. Violating refresh requirements during power-down may result in loss of data. 2. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM CLOCK SUSPEND MODE 1 T0 CLK tCK T1 tCL tCH tCKS tCKH CKE tCKS tCMS COMMAND tCKH tCMH NOP tCMS tCMH DQM3 tAS A0-A9 tAH COLUMN e (A0 - A7)2 T2 T3 T4 T5 T6 T7 T8 T9 READ NOP NOP NOP NOP WRITE NOP COLUMN m (A0 - A7)2 tAS A10 tAS BA tAH tAH BANK tAC tAC tOH DOUT m tLZ DON'T CARE UNDEFINED tHZ DOUT m + 1 tDS tDH DIN e + 1 BANK DQ DIN e TIMING PARAMETERS -6 SYMBOL* tAC (3) tAC (2) tAC (1) tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) tCKH -7 MAX 5.5 8 18 MIN MAX 5.5 8.5 22 MIN MIN -8A MAX 6 9 22 -6 UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL* tCKS tCMH tCMS tDH tDS tHZ (3) tHZ (2) tHZ (1) tLZ tOH -7 MAX MIN 2 1 2 1 2 5.5 6 18 5.5 8.5 22 1 1.5 1 1.5 MAX MIN 2 1 2 1 2 MIN 2 1 2 1 2 -8A MAX UNITS ns ns ns ns ns 1 2 2.5 2.5 6 8 20 1 1 2 2.75 2.75 7 10 25 1 1 2 3 3 8 13 25 1 6 9 22 ns ns ns ns ns 1 1.5 *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled. 2. A8 and A9 = "Don't Care." 3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM AUTO REFRESH MODE T0 CLK tCK T1 T2 tCH (( )) (( )) (( )) Tn + 1 tCL (( )) (( )) (( )) To + 1 CKE tCKS tCMS COMMAND tCKH tCMH NOP AUTO REFRESH NOP PRECHARGE (( )) ( ( NOP )) (( )) (( )) AUTO REFRESH NOP (( )) ( ( NOP )) (( )) (( )) ACTIVE DQM1 tAS ADDRESS tAH BANK(S) (( )) (( )) (( )) tRP tRCAR tRC (( )) (( )) (( )) BANK, ROW DQ High-Z Precharge all active banks. DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) -7 MAX MIN 1 2 2.75 2.75 7 10 25 MAX MIN 1 2 3 3 8 13 25 MIN 1 2 2.5 2.5 6 8 20 -8A MAX -6 UNITS ns ns ns ns ns ns ns SYMBOL* tCKH tCKS tCMH tCMS tRC tRCAR tRP -7 MAX MIN 1 2 1 2 70 70 21 MAX MIN 1 2 1 2 80 80 24 MIN 1 2 1 2 60 66 18 -8A MAX UNITS ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM SELF REFRESH MODE T0 CLK tCK T1 tCH tCL T2 (( )) (( )) Tn + 1 tCKS > tRAS (( )) (( )) (( )) (( )) To + 1 To + 2 CKE tCKS tCKH (( )) tCKS tCMS tCMH COMMAND PRECHARGE NOP AUTO REFRESH (( )) (( )) (( )) (( )) NOP ( ( (( )) AUTO REFRESH )) DQM1 t AS ADDRESS tAH (( )) (( )) BANK(S) (( )) (( )) (( )) (( )) DQ High-Z tRP Precharge all active banks. Enter self refresh mode. (( )) (( )) tXSR Exit self refresh mode. (Restart refresh time base.) CLK stable prior to exiting self refresh mode. DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) -7 MAX MIN 1 2 2.75 2.75 7 10 25 MAX MIN 1 2 3 3 8 13 25 MIN 1 2 2.5 2.5 6 8 20 -8A MAX -6 UNITS ns ns ns ns ns ns ns SYMBOL* tCKH tCKS tCMH tCMS tRAS tRP tXSR -7 MAX MIN 1 2 1 2 42 21 80 MAX MIN 1 2 1 2 48 24 80 MIN 1 2 1 2 42 18 80 -8A MAX UNITS ns ns ns ns ns ns ns 120,000 120,000 120,000 *CAS latency indicated in parentheses. NOTE: 1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM SINGLE READ - WITHOUT AUTO PRECHARGE 1 T0 CLK tCKS CKE tCMS tCMH COMMAND ACTIVE NOP READ tCMS tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAS A10 tAS BA0, BA1 tAH ROW tAH ROW tAH BANK DISABLE AUTO PRECHARGE BANK SINGLE BANKS BANK(S) BANK COLUMN m2 T1 tCK tCKH tCL T2 tCH T3 T4 T5 T6 T7 T8 NOP NOP PRECHARGE NOP ACTIVE NOP ROW ALL BANKS ROW tAC DQ tRCD tRAS tRC tLZ CAS Latency tOH DOUT m tHZ tRP DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAC (3) tAC (2) tAC (1) tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) tCKH tCKS -7 MAX 5.5 8 18 MIN MAX 5.5 8.5 22 MIN -8A MAX 6 9 22 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL* tCMH tCMS tHZ (3) tHZ (2) tHZ (1) tLZ tOH tRAS tRC tRCD tRP -6 MIN 1 2 MAX MIN 1 2 -7 MAX MIN 1 2 MIN -8A MAX 5.5 6 18 1 1.5 42 60 18 18 1 1.5 42 70 20 21 5.5 8.5 22 1 1.5 48 80 24 24 6 9 22 UNITS ns ns ns ns ns ns ns ns ns ns ns 1 2 2.5 2.5 6 8 20 1 2 1 2 2.75 2.75 7 10 25 1 2 1 2 3 3 8 13 25 1 2 120,000 120,000 120,000 *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. A8, A9 = "Don't Care." 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM READ - WITHOUT AUTO PRECHARGE 1 T0 CLK tCKS CKE tCMS tCMH COMMAND ACTIVE NOP READ tCMS tCMH DQM 3 T1 tCK tCKH tCL T2 tCH T3 T4 T5 T6 T7 T8 NOP NOP NOP PRECHARGE NOP ACTIVE tAS A0-A9 tAS A10 tAS BA tAH ROW tAH ROW tAH BANK DISABLE AUTO PRECHARGE BANK tAC tOH DOUT m tAC tOH DOUT m+1 BANK 0 or 1 BANK(S) tAC tOH DOUT m+2 tRP tOH DOUT m+3 tHZ BANK COLUMN m (A0 - A7)2 ROW BANK 0 and 1 ROW tAC DQ tRCD tRAS tRC tLZ CAS Latency DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAC -7 MAX 5.5 8 18 MIN MAX 5.5 8.5 22 1 2 2.75 2.75 7 10 25 1 2 1 2 3 3 8 13 25 1 2 MIN MIN -8A MAX 6 9 22 -6 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL* tCMH tCMS tHZ (3) tHZ (2) tHZ (1) tLZ tOH tRAS tRC tRCD tRP -7 MAX MIN 1 2 5.5 6 18 5.5 8.5 22 1 1 120,000 1.5 48 80 24 24 1.5 42 70 20 21 MAX MIN 1 2 (3) tAC (2) tAC (1) tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) tCKH tCKS MIN 1 2 -8A MAX UNITS ns ns ns ns ns ns ns ns ns ns ns 6 9 22 1 2 2.5 2.5 6 8 20 1 2 1 1.5 42 60 18 18 120,000 120,000 *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. A8 and A9 = "Don't Care." 3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM READ - WITH AUTO PRECHARGE 1 T0 CLK tCKS CKE tCMS tCMH COMMAND ACTIVE NOP READ tCMS tCMH DQM3 tAS A0-A9 tAH COLUMN m (A0 - A7)2 T1 tCK tCKH tCL T2 tCH T3 T4 T5 T6 T7 T8 NOP NOP NOP NOP NOP ACTIVE ROW tAS tAH ROW ENABLE AUTO PRECHARGE ROW A10 ROW tAS tAH BANK tAC tOH DOUT m BA BANK BANK tAC tOH DOUT m + 1 tAC DQ tRCD tRAS tRC tLZ CAS Latency tAC tOH DOUT m + 2 tOH DOUTm + 3 tHZ tRP DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAC (3) tAC (2) tAC tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) tCKH tCKS -7 MAX 5.5 8 18 MIN MAX 5.5 8.5 22 1 2 2.75 2.75 7 10 25 1 2 1 2 3 3 8 13 25 1 2 MIN MIN -8A MAX 6 9 22 -6 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL* tCMH tCMS tHZ (3) tHZ (2) tHZ (1) tLZ tOH tRAS tRC tRCD tRP -7 MAX MIN 1 2 5.5 6 18 5.5 8.5 22 1 1 120,000 1.5 48 80 24 24 1.5 42 70 20 21 MAX MIN 1 2 MIN 1 2 -8A MAX UNITS ns ns ns ns ns ns ns ns ns ns ns (1) 1 2 2.5 2.5 6 8 20 1 2 6 9 22 1 1.5 42 60 18 18 120,000 120,000 *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. A8 and A9 = "Don't Care." 3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM ALTERNATING BANK READ ACCESSES 1 T0 CLK tCKS CKE tCMS tCMH COMMAND ACTIVE NOP READ NOP ACTIVE NOP READ NOP ACTIVE T1 tCK tCKH tCL T2 tCH T3 T4 T5 T6 T7 T8 tCMS tCMH DQM3 tAS A0-A9 tAH COLUMN m (A0 - A7)2 ROW COLUMN b (A0 - A7)2 ROW ROW tAS A10 tAH ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW ROW tAS BA tAH BANK 0 BANK 1 BANK 1 BANK 0 BANK 0 tAC DQ tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRRD tLZ CAS Latency - BANK 0 tAC tOH DOUT m tAC tOH DOUT m + 1 tAC tOH DOUT m + 2 tAC tOH DOUT m + 3 tAC tOH DOUT b tRP - BANK 0 tRCD - BANK 0 tRCD - BANK 1 CAS Latency - BANK 1 DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAC (3) tAC (2) tAC (1) tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) tCKH -7 MAX 5.5 8 18 MIN MAX 5.5 8.5 22 1 2 2.75 2.75 7 10 25 1 1 2 3 3 8 13 25 1 MIN MIN -8A MAX 6 9 22 -6 UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL* tCKS tCMH tCMS tLZ tOH tRAS tRC tRCD tRP tRRD -7 MAX MIN 2 1 2 1 1.5 42 70 20 21 14 MAX MIN 2 1 2 1 1.5 48 80 24 24 16 MIN 2 1 2 1 1.5 42 60 18 18 12 -8A MAX UNITS ns ns ns ns ns ns ns ns ns ns 1 2 2.5 2.5 6 8 20 1 120,000 120,000 120,000 *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. A8 and A9 = "Don't Care." 3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM READ - FULL-PAGE BURST 1 T0 CLK tCKS CKE tCMS COMMAND tCMH NOP READ NOP NOP NOP NOP (( )) (( )) (( )) (( )) T1 tCL tCH tCKH tCK T2 T3 T4 T5 T6 (( )) (( )) Tn + 1 Tn + 2 Tn + 3 Tn + 4 (( )) (( )) ACTIVE NOP BURST TERM NOP NOP tCMS DQM3 tCMH tAS A0-A9 tAH COLUMN m (A0 - A7)2 ROW (( )) (( )) tAS A10 tAH ROW (( )) (( )) tAS BA tAH BANK BANK (( )) (( )) tAC tAC DQ tLZ tOH DOUT m tAC tOH DOUT m+1 tAC ( ( tOH ) ) (( )) DOUT m+2 (( )) tAC tOH DOUT m-1 tAC tOH DOUT m tOH DOUT m+1 tHZ 256 locations within same row. Full page completed. tRCD CAS Latency Full-page burst does not self-terminate. Can use BURST TERMINATE command. 4 DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAC tAC tAC tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) -7 MAX 5.5 8 18 MIN MAX 5.5 8.5 22 1 2 2.75 2.75 7 10 25 1 2 3 3 8 13 25 MIN MIN -8A MAX 6 9 22 -6 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL* tCKH tCKS tCMH tCMS tHZ (3) tHZ (2) tHZ (1) tLZ tOH tRCD -7 MAX MIN 1 2 1 2 5.5 6 18 5.5 8.5 22 1 1.5 20 1 1.5 24 MAX MIN 1 2 1 2 -8A MAX UNITS ns ns ns ns 6 9 22 ns ns ns ns ns ns (3) (2) (1) 1 2 2.5 2.5 6 8 20 MIN 1 2 1 2 1 1.5 18 *CAS latency indicated in parentheses. NOTE: 1. 2. 3. 4. For this example, the CAS latency = 2. A8 and A9 = "Don't Care." DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. Page left open; no tRP. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM READ - DQM OPERATION 1 T0 CLK tCKS CKE tCMS COMMAND tCMH NOP READ NOP NOP NOP NOP NOP NOP T1 tCK tCKH tCL T2 tCH T3 T4 T5 T6 T7 T8 ACTIVE tCMS DQM3 tAS A0-A9 tAH tCMH ROW COLUMN m (A0 - A7)3 ENABLE AUTO PRECHARGE tAS A10 tAH ROW tAS BA tAH BANK DISABLE AUTO PRECHARGE BANK tAC DQ tLZ tRCD CAS Latency tOH DOUT m tAC tAC tOH DOUT m + 2 tOH DOUT m + 3 tHZ tLZ tHZ DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAC -7 MAX 5.5 8 18 MIN MAX 5.5 8.5 22 1 2 2.75 2.75 7 10 25 1 2 3 3 8 13 25 MIN -8A MAX 6 9 22 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL* tCKH tCKS tCMH tCMS tHZ (3) tHZ (2) tHZ (1) tLZ tOH tRCD -6 MIN 1 2 1 2 5.5 6 18 1 1.5 18 1 1.5 20 MAX MIN 1 2 1 2 -7 MAX MIN 1 2 1 2 5.5 8.5 22 1 1.5 24 MIN -8A MAX (3) tAC (2) tAC (1) tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) UNITS ns ns ns 1 2 2.5 2.5 6 8 20 6 9 22 ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. A8 and A9 = "Don't Care." 3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM SINGLE WRITE - WITHOUT AUTO PRECHARGE 1 T0 CLK tCKS CKE tCMS COMMAND tCMH NOP WRITE NOP PRECHARGE NOP ACTIVE tCK tCKH T1 tCL T2 tCH T3 T4 T5 T6 ACTIVE tCMS tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAH COLUMN m 3 ALL BANKS ROW DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK ROW ROW tAS A10 tAH ROW tAS BA0, BA1 tAH BANK tDS DQ tRCD tRAS tRC tDH DIN m t WR 2 tRP DON'T CARE TIMING PARAMETERS -6 SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) tCKH tCKS -7 MAX MIN 1 2 2.75 2.75 7 10 25 1 2 MAX MIN 1 2 3 3 8 13 25 1 2 MIN 1 2 2.5 2.5 6 8 20 1 2 -8A MAX -6 UNITS ns ns ns ns ns ns ns ns ns SYMBOL* tCMH tCMS tDH tDS tRAS tRC tRCD tRP tWR -7 MAX MIN 1 2 1 2 42 70 20 21 10 MAX MIN 1 2 1 2 48 80 24 24 10 MIN 1 2 1 2 42 60 18 18 10 -8A MAX UNITS ns ns ns ns ns ns ns ns ns 120,000 120,000 120,000 *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a "manual" PRECHARGE. 2. 10ns is required between 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM WRITE - WITHOUT AUTO PRECHARGE 1 T0 CLK tCKS CKE tCMS tCMH COMMAND ACTIVE NOP WRITE NOP NOP NOP PRECHARGE NOP ACTIVE tCK tCKH T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 tCMS tCMH DQM3 tAS A0-A9 tAH COLUMN m (A0 - A7)2 BANK 0 and 1 ROW DISABLE AUTO PRECHARGE BANK BANK 0 or 1 BANK(S) BANK ROW ROW tAS A10 tAH ROW tAS BA tAH BANK tDS DQ tRCD tRAS tRC tDH DIN m tDS tDH tDS tDH tDS tDH DIN m + 1 DIN m + 2 DIN m + 3 t WR4 tRP DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) tCKH tCKS -7 MAX MIN 1 2 2.75 2.75 7 10 25 1 2 MAX MIN 1 2 3 3 8 13 25 1 2 -8A MAX UNITS ns ns ns ns ns ns ns ns ns SYMBOL* tCMH tCMS tDH tDS tRAS tRC tRCD tRP tWR -6 MIN 1 2 1 2 42 60 18 18 10 120,000 MAX MIN 1 2 1 2 42 70 20 21 10 -7 MAX MIN 1 2 1 2 120,000 48 80 24 24 10 -8A MAX UNITS ns ns ns ns 120,000 ns ns ns ns ns MIN 1 2 2.5 2.5 6 8 20 1 2 *CAS latency indicated in parentheses. NOTE: 1. 2. 3. 4. For this example, the burst length = 4, and the WRITE burst is followed by "manual" PRECHARGE. A8 and A9 = "Don't Care." DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. Faster frequencies will require two clocks (when tWR > tCK). 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM WRITE - WITH AUTO PRECHARGE 1 T0 CLK tCKS CKE tCMS tCMH COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP ACTIVE tCK tCKH T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 tCMS tCMH DQM3 tAS A0-A9 tAH COLUMN m (A0 - A7)2 ENABLE AUTO PRECHARGE ROW ROW ROW tAS A10 tAH ROW tAS BA tAH BANK BANK BANK tDS DQ tRCD tRAS tRC tDH DIN m tDS tDH tDS tDH tDS tDH DIN m + 1 DIN m + 2 DIN m + 3 tWR4 tRP DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) tCKH tCKS -7 MAX MIN 1 2 2.75 2.75 7 10 25 1 2 MAX MIN 1 2 3 3 8 13 25 1 2 MIN 1 2 2.5 2.5 6 8 20 1 2 -8A MAX -6 UNITS ns ns ns ns ns ns ns ns ns SYMBOL* tCMH tCMS tDH tDS tRAS tRC tRCD tRP tWR -7 MAX MIN 1 2 1 2 MAX MIN 1 2 1 2 120,000 48 80 MIN 1 2 1 2 42 60 18 18 1 + 4ns -8A MAX UNITS ns ns ns ns 120,000 42 70 20 21 1 + 3ns 120,000 ns ns ns ns tCK 24 24 1 + 2ns *CAS latency indicated in parentheses. NOTE: 1. 2. 3. 4. For this example, the burst length = 4. A8 and A9 = "Don't Care." DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. Faster frequencies will require two clocks (when tWR > tCK). 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM ALTERNATING BANK WRITE ACCESSES 1 T0 CLK tCKS CKE tCMS tCMH COMMAND ACTIVE NOP WRITE NOP ACTIVE NOP WRITE NOP ACTIVE tCK tCKH T1 tCL T2 tCH T3 T4 T5 T6 T7 T8 tCMS tCMH DQM3 tAS A0-A9 tAH COLUMN m (A0 - A7)2 ROW COLUMN b (A0 - A7)2 ROW ROW tAS A10 tAH ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW ROW tAS BA tAH BANK 0 BANK 1 BANK 1 BANK 0 BANK 0 tDS DQ tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRRD tDH DIN m tDS tDH tDS tDH tDS tDH tDS tDH DIN b tDS tDH tDS tDH DIN m + 1 DIN m + 2 DIN m + 3 tWR - BANK 04 DIN b + 1 tRP - BANK 0 DIN b + 2 tRCD - BANK 0 tRCD - BANK 1 DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) tCKH tCKS tCMH -7 MAX MIN 1 2 2.75 2.75 7 10 25 1 2 1 MAX MIN 1 2 3 3 8 13 25 1 2 1 MIN 1 2 2.5 2.5 6 8 20 1 2 1 -8A MAX -6 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL* tCMS tDH tDS tRAS tRC tRCD tRP tRRD tWR -7 MAX MIN 2 1 2 MAX MIN 2 1 2 120,000 48 80 24 24 16 MIN 2 1 2 42 60 18 18 12 1 + 4ns -8A MAX UNITS ns ns ns 120,000 42 70 20 21 14 1 + 3ns 120,000 ns ns ns ns ns tCK 1 + 2ns *CAS latency indicated in parentheses. NOTE: 1. 2. 3. 4. For this example, the burst length = 4. A8 and A9 = "Don't Care." DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. Faster frequencies will require two clocks (when tWR > tCK). 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM WRITE - FULL-PAGE BURST T0 CLK tCKS CKE tCMS tCMH COMMAND ACTIVE NOP WRITE NOP NOP NOP T1 tCL tCH tCKH tCK T2 T3 T4 T5 (( )) (( )) Tn + 1 Tn + 2 Tn + 3 (( )) (( )) (( )) (( )) NOP BURST TERM NOP tCMS tCMH DQM 2 (( )) (( )) tAS A0-A9 tAH COLUMN m (A0 - A7)1 ROW (( )) (( )) tAS A10 tAH ROW (( )) (( )) tAS BA tAH BANK BANK (( )) (( )) tDS DQ tRCD tDH DIN m tDS tDH tDS tDH tDS tDH DIN m + 1 DIN m + 2 DIN m + 3 (( )) (( )) tDS tDH tDS tDH DIN m - 1 256 locations within same row. Full page completed. Full-page burst does not self-terminate. Can use 3 BURST TERMINATE command. DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) -7 MAX MIN 1 2 2.75 2.75 7 10 25 MAX MIN 1 2 3 3 8 13 25 MIN 1 2 2.5 2.5 6 8 20 -8A MAX -6 UNITS ns ns ns ns ns ns ns SYMBOL* tCKH tCKS tCMH tCMS tDH tDS tRCD -7 MAX MIN 1 2 1 2 1 2 20 MAX MIN 1 2 1 2 1 2 24 MIN 1 2 1 2 1 2 18 -8A MAX UNITS ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. A8 and A9 = "Don't Care." 2. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. 3. Page left open; no tRP. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM WRITE - DQM OPERATION 1 T0 CLK tCKS CKE tCMS tCMH COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP T1 tCK tCKH tCL T2 tCH T3 T4 T5 T6 T7 tCMS tCMH DQM 3 tAS A0-A9 tAH COLUMN m (A0 - A7)2 ENABLE AUTO PRECHARGE ROW tAS A10 tAH ROW tAS BA tAH DISABLE AUTO PRECHARGE BANK BANK tDS DQ tRCD tDH DIN m tDS tDH tDS tDH DIN m + 2 DIN m + 3 DON'T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL* tAH tAS tCH tCL tCK (3) tCK (2) tCK (1) -7 MAX MIN 1 2 2.75 2.75 7 10 25 MAX MIN 1 2 3 3 8 13 25 MIN 1 2 2.5 2.5 6 8 20 -8A MAX -6 UNITS ns ns ns ns ns ns ns SYMBOL* tCKH tCKS tCMH tCMS tDH tDS tRCD -7 MAX MIN 1 2 1 2 1 2 20 MAX MIN 1 2 1 2 1 2 24 MIN 1 2 1 2 1 2 18 -8A MAX UNITS ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4. 2. A8 and A9 = "Don't Care." 3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 16Mb: x16 IT SDRAM 50-PIN PLASTIC TSOP (400 mil) C-4 21.04 20.88 0.88 0.10 (2X) 50 2.80 11.86 11.66 10.21 10.11 SEE DETAIL A 1 0.80 TYP 25 0.45 0.30 R 0.75 (2X) R 1.00 (2X) 0.25 GAGE PLANE 0.10 1.2 MAX 0.25 0.05 0.18 0.13 PIN #1 ID 0.60 0.40 DETAIL A 0.80 TYP NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.01" per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 16Mb: x16 IT SDRAM 16MSDRAMx16IT.p65 - Rev. 5/99 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc. 51 |
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